Memory devices are typically used for storing data and are essential for any computing system. With the rise in mobile computing devices (e.g., smartphones, Personal Digital Assistants (PDAs), pocket computers, tablet computers, etc.), it is preferred to have small memory devices that can hold large amounts of data. Several techniques have been introduced to make memory devices smaller with increased storing capability. One such memory device is a Dynamic Random Access Memory (DRAM) device.
A DRAM device (or simply “DRAM”) is often employed for its architectural simplicity; for example, DRAMs employ extremely small capacitors such that billions of them can fit on a single memory chip. DRAM is volatile memory, meaning that it quickly loses its data when power is removed. Also, since a DRAM stores each bit of data in a separate capacitor within an integrated circuit, each capacitor can be charged or discharged. These two steps of charging and discharging represent the two values of a bit, which are typically known as 0 and 1. Since capacitors are known for leaking charge, the stored data eventually fades unless the capacitor charge is refreshed periodically. It is this periodic refresh requirement for DRAMs that the word “dynamic” of DRAM refers to as opposed to the word “static” in Static RAM (SRAM).
Current DRAM devices use refresh operations to maintain the state of each cell of memory over time. A DRAM cell programmed to “1” will decay over time and eventually be unable to distinguish between a one and a zero. In order to ensure that cells maintain their value, the frequency of refresh operations needs to be higher than the decay time. For example, the frequency of refresh operations need be high enough to ensure that any cell has a probability of error of less than 10−18. Complicating matters, cell decay is temperature-dependent and for each 10 degrees Celcius of temperature increase, the average decay time for a cell reduces by half. Even worse, future memory devices may be placed directly above a System-on-a-Chip (SoC), which can result in different parts of the DRAM device being exposed to different temperatures. A conventional system for determining decay uses a single temperature sensor that may be inaccurate and/or far from the ‘hot spot’ on the DRAM device. Using this single temperature sensor requires a highly conservative policy that takes the worst-case temperature into account and causes the DRAM to be refreshed at the worst-case rate. This results in higher power consumption, less available bandwidth, and remains far from the optimal refresh rate.
According to one conventional technique, as illustrated in prior art FIG. 2D, a temperature sensor is placed on a memory array of a DRAM device and a temperature sensor readout is then used to determine the refresh policy for the entire array. There are severe limtiations with this approach. For example, the temperature sensor readout can be inaccurate due to process variation, placement of the sensor within the array, or limitations of the temperature sensor design (e.g., quantization, etc.). In addition, a DRAM takes the worst case (temperature) scenario in account when determining a refresh policy. Thus, with a temperature sensor with an accuracy of +/−5 degrees Celsius and a maximum temperature gradient of 5 degrees Celsius across the memory array, the refresh policy must take into account the possibility of a total of 10 degrees Celsius difference between the temperature readout and any given cell in the memory array. This results in an overly conservative approach for refresh operations and also, increases the amount of power that the system consumes to perform the refresh policy, and limits the available system bandwidth because the memory array is unavailable during refresh periods. Additionally, heating caused by excessive refresh operations exacerbates the problem.
Furthermore, an increase in the density of a DRAM device causes an increase in the number of refresh operations for that device. Consequently, using conventional refresh schemes, future DRAMs may require up to 25% of the DRAM bandwidth to be dedicated to refresh operations due to density and temperature increases. According to certain data reports, with the increase in DRAM density and temperature, the bandwidth utilization of refresh operations can grow from the best case scenario of 3% to the worst case senario of 86%.